Dispositivos Analógicos Programables

Introducción a los dispositivos programables anal ógicos. Dispositivos TRAC, ispPAC y Anadigm: arquitectura,interconexiones, macros, fases de diseño, software de diseño, etc. Aplicacione

Ventricular Fibrillation and Tachycardia Detection Using Features Derived from Topological Data Analysis

A rapid and accurate detection of ventricular arrhythmias is essential to take appropriate therapeutic actions when cardiac arrhythmias occur. Furthermore, the accurate discrimination between arrhythmias is also important, provided that the required shocking therapy would not be the same. In this work, the main novelty is the use of the mathematical method known as Topological Data Analysis (TDA) to generate new types of features which can contribute to the improvement of the detection and classification performance of cardiac arrhythmias such as Ventricular Fibrillation (VF) and Ventricular Tachycardia (VT). The electrocardiographic (ECG) signals used for this evaluation were obtained from the standard MIT-BIH and AHA databases. Two input data to the classify are evaluated: TDA features, and Persistence Diagram Image (PDI). Using the reduced TDA-obtained features, a high average accuracy near 99% was observed when discriminating four types of rhythms (98.68% to VF; 99.05% to VT; 98.76% to normal sinus; and 99.09% to Other rhythms) with specificity values higher than 97.16% in all cases. In addition, a higher accuracy of 99.51% was obtained when discriminating between shockable (VT/VF) and non-shockable rhythms (99.03% sensitivity and 99.67% specificity). These results show that the use of TDA-derived geometric features, combined in this case this the k-Nearest Neighbor (kNN) classifier, raises the classification performance above results in previous works. Considering that these results have been achieved without preselection of ECG episodes, it can be concluded that these features may be successfully introduced in Automated External Defibrillation (AED) and Implantable Cardioverter Defibrillation (ICD) therapie

New algorithm for fetal QRS detection in surface abdominal records

The proposed method detects fetal R waves on abdominal non-invasive records. An exponentially averaged pattern of the mother PQRST segment is obtained and subtracted. Subsequently the fetal R detector based on a Smoothed Nonlinear Energy Operator (SNEO) is applied to the residual signal. Finally, criteria about amplitude, heart rate and backward search are settled to correct false detections. To evaluate the fetal R detector, 10 multichannel records were used, acquired between gestation week 22 and 40. The position of the fetal R waves were manually marked (N=1490), and these reference marks were compared with the ones from the detector. It was obtained a 88.83% of sensitivity and a 91.32% of positive prediction value. The application of the detector to all the abdominal channels will probably allow improving the obtained results

An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations' performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication. The proposed architecture is fully scalable with the maximum matrix dimension limited by the available resources. In addition, a design environment is also developed, permitting assistance, through a friendly interface, from the customization of the hardware computing unit to the generation of the final synthesizable IP core. For N x N matrices, the architecture requires N ALU-RAM blocks and performs O(N*N), requiring N*N +7 and N +7 clock cycles for matrix-matrix and matrix-vector operations, respectively. For the tested Virtex7 FPGA device, the computation for 500 x 500 matrices allows a maximum clock frequency of 346 MHz, achieving an overall performance of 173 GOPS. This architecture shows higher performance than other state-of-the-art matrix computing units

Aprendizaje por Proyectos: Una Aproximación Docente al Diseño Digital Basado en VHDL

Abstract-- Digital design based on hardware description languages is difficult for students, especially when the course covers from basics to advanced design systems and hardware implementation topics. This paper describes the proposal of a course where students have basic knowledge in digital design but null knowledge in hardware description languages as VHDL and FPGA (Field Programmable Gate Array) devices. Using Project Based Learning (PBL), this proposal allows increasing the learning curve, improving motivation and achieving some of the indications given by the European High Education Area (EHEA)

Análisis tiempo-frecuencia de mapas de activación cardíaca en fibrilación ventricular

El análisis de mapas de activación permite investigar la estructura de la fibrilación ventricular cardíaca (FV). El presente trabajo plantea una revisión de la utilización de objetos de interés (blobs), usados en procesado de imágenes y aplicados también a mapas de activación cerebral y cardíaca, mediante su generación a partir de representaciones tiempo-frecuencia de registros FV. Su estudio proporciona información sobre qué frecuencias de la señal están presentes en un instante dado, así como su distribución espacial. También permiten determinar el momento en que una determinada frecuencia aparece y desaparece de cada electrodo, por lo que constituye una herramienta interesante para analizar los mecanismos de generación y mantenimiento de la FV

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in layers, and a number of layers. The hardware combines matrix algebra concepts with serial-parallel computation. It is based on a systolic ring of neural processing elements (NPE), only requiring as many NPEs as neuron units in the largest layer, no matter the number of layers. The use of resources grows linearly with the number of NPEs. This versatile architecture serves as an accelerator in real-time applications and its size does not affect the system clock frequency. Unlike most approaches, a single activation function block (AFB) for the whole FFNN is required. Performance, resource usage, and accuracy for several network topologies and activation functions are evaluated. The architecture reaches 550 MHz clock speed in a Virtex7 FPGA. The proposed implementation uses 18-bit fixed point achieving similar classification performance to a floating point approach. A reduced weight bit size does not affect the accuracy, allowing more weights in the same memory. Different FFNN for Iris and MNIST datasets were evaluated and, for a real-time application of abnormal cardiac detection, a x256 acceleration was achieved. The proposed architecture can perform up to 1980 Giga operations per second (GOPS), implementing the multilayer FFNN of up to 3600 neurons per layer in a single chip. The architecture can be extended to bigger capacity devices or multi-chip by the simple NPE ring extension

NeuroLab: Sistema de adquisición y análisis de registros neurofisiológicos

El registro de la actividad eléctrica extracelular constituye el método principal de análisis del comportamiento y función de neuronas y redes neuronales en estudios experimentales invasivos. Se describe un nuevo programa, NeuroLab, desarrollado para la adquisición, visualización y análisis de este tipo de registros. Permite obtener ficheros de hasta 16 canales de campo, unitarios y estimulación. Se han incluido funciones básicas para facilitar al usuario la comprobación de la adquisición correcta, tanto durante la misma (reproducción visual y acústica) como posteriormente mediante opciones de procesado digital. Su concepción modular permite incrementar sus prestaciones añadiendo nuevas funciones a las ya existentes, y el procesado posterior de los datos adquiridos amplía las posibilidades de análisis de este tipo de estudios frente a soluciones comerciales cerradas

Clasificación de registros de mapeado cardíaco en fibrilación ventricular

El presente trabajo estudia las modificaciones intrínsecas que el ejercicio físico produce en la respuesta cardíaca durante fibrilación ventricular (FV). Para ello se plantea el desarrollo de clasificadores (RL; regresión logística y ELM; Extreme Learning Machine) que diferencien entre el grupo control y los sujetos entrenados. Como parámetros de entrada a los clasificadores se han considerado dos relacionados con el espectro de la señal (FD: frecuencia dominante, y EN: energía normalizada), y otros relacionados con la regularidad y organización de las ondas de activación local, OAL, (IR: índice de regularidad y NO: número de ocurrencias). Se ha realizado un análisis de regiones de interés (ROI) de los tres primeros parámetros para valorar su uniformidad espacial. El trabajo tiene un doble objetivo: estudiar las capacidades de los distintos clasificadores y obtener información acerca de la importancia de las variables a la hora de realizar la clasificación. Se analizaron registros de mapeado cardíaco correspondientes a dos grupos: control (G1: sin entrenamiento, N=10) y entrenados (G2, N=9). Del estudio de las capacidades de ambos clasificadores, se puede observar cómo la ELM obtiene mejores índices de funcionamiento que la RL. Si se analiza el producto sensibilidad por especificidad en el conjunto de validación, se obtiene un 60.73% con la RL y un 72.37% con la ELM. En cuanto al análisis de variables, los resultados obtenidos sugieren que los cambios intrínsecos en FV debidos al ejercicio físico están relacionados con la regularidad morfológica y la uniformidad espectral de las señales de activación del tejido cardíaco

Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm

Currently, there are some emerging online learning applications handling data streams in real-time. The On-line Sequential Extreme Learning Machine (OS-ELM) has been successfully used in real-time condition prediction applications because of its good generalization performance at an extreme learning speed, but the number of trainings by a second (training frequency) achieved in these continuous learning applications has to be further reduced. This paper proposes a performance-optimized implementation of the OS-ELM training algorithm when it is applied to real-time applications. In this case, the natural way of feeding the training of the neural network is one-by-one, i.e., training the neural network for each new incoming training input vector. Applying this restriction, the computational needs are drastically reduced. An FPGA-based implementation of the tailored OS-ELMalgorithm is used to analyze, in a parameterized way, the level of optimization achieved. We observed that the tailored algorithm drastically reduces the number of clock cycles consumed for the training execution up to approximately the 1%. This performance enables high-speed sequential training ratios, such as 14 KHz of sequential training frequency for a 40 hidden neurons SLFN, or 180 Hz of sequential training frequency for a 500 hidden neurons SLFN. In practice, the proposed implementation computes the training almost 100 times faster, or more, than other applications in the bibliography. Besides, clock cycles follows a quadratic complexity O(N 2), with N the number of hidden neurons, and are poorly influenced by the number of input neurons. However, it shows a pronounced sensitivity to data type precision even facing small-size problems, which force to use double floating-point precision data types to avoid finite precision arithmetic effects. In addition, it has been found that distributed memory is the limiting resource and, thus, it can be stated that current FPGA devices can support OS-ELM-based on-chip learning of up to 500 hidden neurons. Concluding, the proposed hardware implementation of the OS-ELM offers great possibilities for on-chip learning in portable systems and real-time applications where frequent and fast training is required